1. Field of the Invention
This invention relates to high density ROM memories and more particularly to improved word and bit line structures.
2. Description of Related Art
FIG. 1 shows a prior art device 10 including a semiconductor substrate 11 composed of P- doped silicon with buried N+ BN+ layer 14, 18 in the substrate 11. BN+ bit lines 14 are oriented vertically. The substrate 11 is covered with gate oxide layer as is well understood by those skilled in the art. A plurality of polysilicon word lines 15 are formed upon the surface of the substrate oriented orthogonally to the buried bit lines. Parallel with the word lines 15 is a select transistor line 16 which slightly overlaps the buried bit lines 14 and BN+ region 18 which comprises an active contact area. A bit line contact 20 is provided for connection between bit line 12 and BN+ active contact 18. As can be seen, the buried N+ regions are formed before the gate oxide layer and before the deposition of the Polysilicon lines 15. To achieve high density memory structures with the design of FIG. 1 it is necessary to shrink the width of the buried bit lines 14. Avoidance of the possibility punchthrough requires additional buried N+ dopant. The result of the narrowing of the bit lines 14 is that the sheet resistance is increased, so more contact area is required to decrease the bit line resistance R.sub..congruent. for the cells to pick up the cell signal. But the increase in contact area increases the effective cell size.
BN+ formation before the gate oxide and polysilicon deposition is a very early step. For high density, BN+ width will shrink and punchthrough issue so BN+ dopant also decreases. BN+ sheet resistance is more severe so more bit line contact is needed. The bit line R.sub..congruent. is reduced to pick up the cell signal. This increases the effective cell size.
There are at least two major problems of ROM devices with buried N+ (BN+) regions of the variety shown in FIG. 1. One of the problems is higher BN+ sheet resistance 5.about.200 .OMEGA./.congruent., so usually there is a bit line pickup every .about.32 word lines, so the effective cell size is increased due to the bit line contact and select transistor area shared by of the bit line contact and select transistor.
The second issue is the problem of BN+ to BN+ punchthrough, due to N+ dopant diffusion.
The improvement provided by this invention is use of a second conductor (polysilicon, polycide, refractory metal, or metal) for bit line instead of BN+ to resolve the issues pertaining to the sheet resistance and the punchthrough problems.
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U.S. Pat. No. 4,898,840 of Okuyama for "Semiconductor Integrated Circuit Device and a Method of Producing the Same",
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U.S. Pat. No. 5,149,664 of Shin et al for "Self-Aligning Ion Implantation Method for Semiconductor Device Having Multi-Gate Type MOS Transistor Structure"
FIGS. 4A and 4B show a prior art conventional buried N+ ROM cell 10 with a P- semiconductor substrate 11, polysilicon 1 lines 15, buried bit lines 14 and current line 17 from the high voltage bit line 14 through line 15 to the lower voltage bit line 14. The gate oxide 13 is located between the buried bit lines 14 and the polysilicon 1 lines 15. The disadvantage of the design of FIGS. 4A and 4B is that there is a high buried N+ resistance. In addition, the BN+ to BN+ punchthrough voltage is a problem as stated above.